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Formal-analysis-based trace computation for post-silicon debug
Marcel Gort,
Flavio M. De Paula,
Johnny J. W. Kuan,
Tor M. Aamodt,
Alan J. Hu,
Steven J. E. Wilton,
Jin Yang
November 2012
IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Volume 20 Issue 11, November 2012
Publisher: IEEE Educational Activities Department
This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is presented that considers practical considerations such as area, on-chip non-determinism ...
Keywords:
hardware breakpoint, formal analysis, post-silicon debug, silicon debug, validation
2
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Assem A.M. Bsoul,
Steven J.E. Wilton
February 2012
FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 3, Downloads (12 Months): 8, Downloads (Overall): 219
Full text available:
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A dynamically-controlled power-gated (DCPG) FPGA architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If ...
Keywords:
architecture, inrush current, leakage power, FPGA, power gating
3
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition
Jeffrey B. Goeders,
Guy G. F. Lemieux,
Steven J. E. Wilton
November 2011
RECONFIG '11: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Publisher: IEEE Computer Society
As each generation of FPGAs grow in size, the run time of the associated CAD tools is rapidly increasing. Many past efforts have aimed at improving the CAD run time through parallelization of the placement algorithm. Wang and Lemieux presented an algorithm that is scalable, deterministic, timing-driven and achieves speedup ...
Keywords:
FPGA, CAD, parallel placement
4
An analytical model relating FPGA architecture parameters to routability
Joydip Das,
Steven J.E. Wilton
February 2011
FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1, Downloads (12 Months): 12, Downloads (Overall): 541
Full text available:
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We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to ...
Keywords:
fpga, analytical model, architecture development, routability
5
Towards scalable FPGA CAD through architecture
Scott Y.L. Chin,
Steven J.E. Wilton
February 2011
FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2, Downloads (12 Months): 13, Downloads (Overall): 253
Full text available:
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Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs ...
Keywords:
fpga, field-programmable gate arrays, architecture, cad run-time
6
Towards analytical methods for FPGA architecture investigation
Steven J. E. Wilton
March 2010
ARC'10: Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Publisher: Springer-Verlag
In the past 20 years, the capacity of FPGAs has grown by 200x and the speed has increased by 40x. Much of this dramatic improvement has been the result of architectural improvements. FPGA architectural enhancements are often developed in a somewhat ad-hoc manner. Expert FPGA architects perform experiments in which ...
7
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)
Usman Ahmed,
Guy G.F. Lemieux,
Steven J.E. Wilton
February 2010
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1, Downloads (12 Months): 9, Downloads (Overall): 218
Full text available:
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In this paper, we evaluate the performance of an FPGA-like interconnect fabric for structured ASICs which is based upon fixed metal and programmable vias. We call this type of device a via-programmed structured ASIC or VPSA. We look at two different types of VPSA routing fabrics: one uses jumper wiring ...
Keywords:
structured asics, via programmable fabric
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Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms
Sohaib Majzoub,
Resve Saleh,
Steven J. E. Wilton,
Rabab Ward
October 2009
SOC'09: Proceedings of the 11th international conference on System-on-chip
Publisher: IEEE Press
In this paper, we propse a novel approach to voltage island formation and core placement for energy optimization in manycore architectures under parameter variation at pre-fabrication stage. We group the cores into irregular "cloud-shaped" valtage islands. The island are created by balancing the desire to limit the spatial extent of ...
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Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Alastair M. Smith,
Steven J.E. Wilton,
Joydip Das
February 2009
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 3, Downloads (12 Months): 22, Downloads (Overall): 453
Full text available:
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This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to ...
Keywords:
architecture design, wirelength estimation, fpga modeling, fpga
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Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
Scott Y. L. Chin,
Steven J. E. Wilton
January 2009
ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 1 Issue 4, January 2009
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1, Downloads (12 Months): 9, Downloads (Overall): 367
Full text available:
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This article presents techniques to reduce the static and dynamic memory requirements of routing algorithms that target field-programmable gate arrays. During routing, memory is required to store both architectural data and temporary routing data. The architectural data is static, and provides a representation of the physical routing resources and programmable ...
Keywords:
CAD, routing, scalability, memory, FPGA
11
BackSpace: Moving Towards Reality
Flavio M. De Paula,
Marcel Gort,
Alan J. Hu,
Steven J. E. Wilton
December 2008
MTV '08: Proceedings of the 2008 Ninth International Workshop on Microprocessor Test and Verification
Publisher: IEEE Computer Society
In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some onchip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a ...
Keywords:
Post-Silicon Debug, Formal Verification, Design-for-Debug
12
BackSpace: formal analysis for post-silicon debug
Flavio M. De Paula,
Marcel Gort,
Alan J. Hu,
Steven J. E. Wilton,
Jin Yang
November 2008
FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 1, Downloads (12 Months): 10, Downloads (Overall): 179
Full text available:
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Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse. We introduce a new paradigm for using formal analysis, augmented with ...
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On the trade-off between power and flexibility of FPGA clock networks
Julien Lamoureux,
Steven J. E. Wilton
September 2008
ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 1 Issue 3, September 2008
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 1, Downloads (12 Months): 12, Downloads (Overall): 362
Full text available:
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FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter ...
Keywords:
clock distribution networks, clock-aware placement, FPGA, low-power design
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A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
Steven J.E. Wilton,
Chun Hok Ho,
Bradley Quinton,
Philip H.W. Leong,
Wayne Luk
March 2008
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs: Volume 1 Issue 1, March 2008
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2, Downloads (12 Months): 5, Downloads (Overall): 527
Full text available:
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We present an architecture for a synthesizable datapath-oriented FPGA core that can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. The primary motivation ...
Keywords:
integrated circuit, Field programmable gate array, silicon debug, system-on-chip
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On the power dissipation of embedded memory blocks used to implement logic in field-programmable gate arrays
Scott Y. L. Chin,
Clarence S. P. Lee,
Steven J. E. Wilton
January 2008
International Journal of Reconfigurable Computing - Regular issue: Volume 2008, January 2008
Publisher: Hindawi Limited
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1, Downloads (12 Months): 1, Downloads (Overall): 54
Full text available:
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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the ...
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A synthesizable datapath-oriented embedded FPGA fabric
Steve J. E. Wilton,
C. H. Ho,
Philip H. W. Leong,
Wayne Luk,
Brad Quinton
February 2007
FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 2, Downloads (12 Months): 7, Downloads (Overall): 399
Full text available:
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We present an architecture for a synthesizable datapath-oriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which ...
Keywords:
embedded block, synthesis, system-on-chip, datapath, field programmable gate array, integrated circuit
17
GlitchLess: an active glitch minimization technique for FPGAs
Julien Lamoureux,
Guy G. Lemieux,
Steven J. E. Wilton
February 2007
FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 1, Downloads (12 Months): 16, Downloads (Overall): 398
Full text available:
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This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the ...
Keywords:
field-programmable gate arrays, power minimization
18
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
C. H. Ho,
P. H. W. Leong,
W. Luk,
S. J. E. Wilton,
S. Lopez-Buedo
April 2006
FCCM '06: Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Embedded elements, such as block multipliers, are increasingly used in advanced field programmable gate array (FPGA) devices to improve efficiency in speed, area and power consumption. A methodology is described for assessing the impact of such embedded elements on efficiency. The methodology involves creating dummy elements, called Virtual Embedded blocks ...
19
FPGA clock network architecture: flexibility vs. area and power
Julien Lamoureux,
Steven J. E. Wilton
February 2006
FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 11
Downloads (6 Weeks): 4, Downloads (12 Months): 21, Downloads (Overall): 719
Full text available:
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This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for Field-Programmable Gate Arrays (FPGA's). The paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global ...
Keywords:
clock network, low-power, FPGA, architecture
20
Routing architecture optimizations for high-density embedded programmable IP cores
Peter Hallschmid,
Steve J. E. Wilton
November 2005
IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Volume 13 Issue 11, November 2005
Publisher: IEEE Educational Activities Department
Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities and show ...
Keywords:
field programmable gate arrays (FPGAs), Field programmable gate arrays (FPGAs), routing, programmable logic devices
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